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LP5030 データシート(PDF) 60 Page - Texas Instruments |
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LP5030 データシート(HTML) 60 Page - Texas Instruments |
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60 / 62 page  www.ti.com EXAMPLE BOARD LAYOUT 0.05 MIN ALL SIDES 0.05 MAX ALL AROUND 46X (0.2) 46X (0.55) ( 0.2) TYP VIA 42X (0.4) (5.85) (4.85) (2.8) (R0.05) TYP (1.01) TYP (0.64) TYP (1.1) TYP (3.8) VQFN - 1 mm max height RJV0046A PLASTIC QUAD FLATPACK - NO LEAD 4223948/B 01/2018 SYMM 1 13 14 23 24 36 37 46 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 47 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL |
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