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LP5569 データシート(PDF) 62 Page - Texas Instruments |
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LP5569 データシート(HTML) 62 Page - Texas Instruments |
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62 / 93 page  62 LP5569 SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 62. ENGINE1_PROG_START Register Field Descriptions Bit Field Type Reset Description 7–0 prog_start_addr1 R/W 0h Engine 1 program start address. 8.6.1.48 ENGINE2_PROG_START Register (Address = 4Ch) [reset = 0h] ENGINE2_PROG_START is shown in Figure 74 and described in Table 63. Return to Summary Table. Engine2 Program Start Register Figure 74. ENGINE2_PROG_START Register 7 6 5 4 3 2 1 0 prog_start_addr2 R/W-0h Table 63. ENGINE2_PROG_START Register Field Descriptions Bit Field Type Reset Description 7–0 prog_start_addr2 R/W 0h Engine 2 program start address. 8.6.1.49 ENGINE3_PROG_START Register (Address = 4Dh) [reset = 0h] ENGINE3_PROG_START is shown in Figure 75 and described in Table 64. Return to Summary Table. Engine3 Program Start Register Figure 75. ENGINE3_PROG_START Register 7 6 5 4 3 2 1 0 prog_start_addr3 R/W-0h Table 64. ENGINE3_PROG_START Register Field Descriptions Bit Field Type Reset Description 7–0 prog_start_addr3 R/W 0h Engine 3 program start address. 8.6.1.50 PROG_MEM_PAGE_SELECT Register (Address = 4Fh) [reset = 0h] PROG_MEM_PAGE_SELECT is shown in Figure 76 and described in Table 65. Return to Summary Table. Program Memory-Page Selection Register SRAM page select. SRAM is 256 × 16 addressable from I2C, and is viewed as 16 pages of 32 bytes. This register selects which page is being accessed, serving as the upper bits of the SRAM address. The I2C host must write this register during the course of loading SRAM contents in order to access the next page. Figure 76. PROG_MEM_PAGE_SELECT Register 7 6 5 4 3 2 1 0 RESERVED page_sel R/W-0h R/W-0h |
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