IS25LE128E-RGLA3:P-TY datasheet(23/197 Pages) ISSI

データシートサーチシステム

IS25LE128E-RGLA3:P-TY データシート(PDF) 23 Page - Integrated Silicon Solution, Inc

部品番号	IS25LE128E-RGLA3:P-TY

部品情報	SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	197 Pages

Scroll/Zoom	100%

メーカー	ISSI [Integrated Silicon Solution, Inc]

ホームページ	http://www.issi.com

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23 / 197 page

IS25LE256E/128E

IS25WE256E/128E

Integrated Silicon Solution, Inc.- www.issi.com

Rev.A9

03/07/2023

WEL bit: Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When WEL bit

is “0”,

the internal write enable latch is disabled and the Write operations described in Table 6.3 are inhibited. When WEL

bit

is “1”, the Write operations are allowed. WEL bit is set by a Write Enable (WREN, 06h) instruction. Most of Write

Non-Volatile/Volatile Register, Program and Erase instruction must be preceded by a WREN instruction.

WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of any

Write Non-Volatile Register, Program and Erase operation.

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