ICS1523MLF datasheet(13/21 Pages) IDT

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Video Clock Synthesizer with I2C Programmable Delay

MDS ICS1523 Z

Revision 052407

Integrated Device Technology, Inc.

Tech Support: www.idt.com/go/clockhelp

ICS1523

11.2 Programming Flow for Modifying PLL and DPA Settings

BEGIN

Determine Horizontal Total

HTOTAL

Program Input Control Register Reg0x0

Typically = 41h

(Coast disabled, Positive edge of HSYNC, Internal Feedback,

FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin

Program DPA Reg0x5

DPA Resolution 0x5 = (Value From Note 8 Table)

DPA Offset, 0x4:5~0 = 0

Full S/W Reset

Reg0xA = 5Ah

Correct Phase

Relationship?

Decrement Charge

Pump Current

Reg0x1:2~0

END

Program Feedback Divider Reg0x2, Reg0x3

Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8

Program Loop Control Register Reg0x1

VCO Divider 0x1:5~4 = (Maximum value where

Required Output Frequency * VCOD < 500 MHz)

Typical Charge Pump Current 0x1:2~0= 011b

Program Output Control Reg0x6

Enable the desired outputs

Program OSC Divider Reg0x7

Select Desired Input Reg0x7:7

Select OSC divider value (if needed)

Increment DPA

Offset

Reg0x4

Program Internal Filter Reg0x4

Select Internal Filter 0x4:7 = 1

Yes

PLL LOCKED?

LOCK Pin or

Read 0x12:1

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