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L99LDLH32 データシート(PDF) 28 Page - STMicroelectronics |
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L99LDLH32 データシート(HTML) 28 Page - STMicroelectronics |
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28 / 142 page  Functional description L99LDLH32 28/142 DS12879 Rev 6 Figure 8. PWM concept for DIN function group The PWM frequency and phase relation of several devices can be synchronized versus each other through the SYNC_I/O pin. There is one dedicated bit (SYNC I/O_M/S - see FTP/RAM memory map, Chapter 7) to configure the device in Provider [1] or Consumer [0] mode. In Provider mode, the Clock frequency with scaler and phase signal is transferred to the SYNC_I/O line. In Consumer mode, clock frequency and phase signal on the SYNC_I/O line are used to synchronize its own clock. Consequently the phase relation among several DIN_EN= [0]? Yes Duty cycle applied on OUTx (1) <=PWM_DUTY_CHx * PWM_DUTY_ALL (2) <= PWM_FREQ_DIN (3) <= duty applied DIN timeout reset DIN timeout & DIN = [0]? Duty cycle applied on OUTx Yes (1) <=PWM_DUTY_CHx * PWM_DUTY_ALL (2) <= PWM_FREQ_DIN (3) <= duty applied No No DIN timeout & DIN = [1]? Yes Outx on DIN timeout_not & DIN = [1]? No Outx on No DIN timeout_not & DIN = [0] Outx off DIN timeout: DIN = [0] > 10ms DIN_EN = [1] DIN DIN timeout Outx 32us delay DIN timeout DIN DIN timeout Outx 32us delay DIN timeout Yes Bus Control DIN Control Bus Control Duty cycle applied on OUTx 32us delay (1) <=PWM_DUTY_CHx * PWM_DUTY_ALL (2) <= PWM_FREQ_DIN (3) <= duty applied (1) <=don’t care (2) <= don’t care (3) <= 1 (100%) (1) <=don’t care (2) <= don’t care (3) <= 1 (100%) (1) <=don’t care (2) <= don’t care (3) <= 0 (0%) |
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