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ICS85411AMI REV. B NOVEMBER 7, 2007

ICS85411I

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

DD

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

DD

= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLK

nCLK

VDD

LVDS

All unused LVDS output pairs can be either left floating or

terminated with 100

Ω across. If they are left floating, there

should be no trace attached.