AD4081BBCZ datasheet(49/95 Pages) AD

49 / 95 page

Data Sheet

AD4081

DIGITAL INTERFACE

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Rev. 0 | 49 of 95

This feature allows the user to align and test the data interface to

their digital host. When the INTF_CHK_EN bit is unset, the normal

conversion results are output to the LVDS interface immediately.

This method is useful for alignment, particularly for self clock mode

cases where unknown PCB propagation delays may be present

between the AD4081 and its digital host controller. Note that this

feature was specifically designed to help output LVDS data with the

LVDS clock of the digital host by using static data, and the feature

does not indicate if the LVDS_CNV_CLK_CNT setting is used.

Table 21. LVDS_CNV_CLK_CNT Settings for Various Sample Rates (with gain correction applied)

Sample Rate (MSPS)

LVDS Lanes

fCLK (MHz)

tCLK (ns)

(tMSB/tCLK) + 1.5

LVDS_CNV_CLK_CNT Setting

200

5.000

5.98

150

6.67

4.86

100

10.000

3.74

20.000

2.62

100

10.000

3.74

AD4081BBCZ データシート(PDF) 49 Page - Analog Devices

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