Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

1

9

1

Frame 3 Data Byte 1

ACK By

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

1

0

0

(1)

R/W

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

Stop By

Master

TMP451

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SBOS686A – JUNE 2013 – REVISED DECEMBER 2014

Programming (continued)

7.5.1.1 Bus Overview

The TMP451 device is SMBus interface compatible. In SMBus protocol, the device that initiates the transfer is

called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master

device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP

conditions.

To address a specific device, a START condition is initiated. A START condition is indicated by pulling the data

line (SDA) from a high-to-low logic level while SCL is high. All slaves on the bus shift in the slave address byte,

with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave

being addressed responds to the master by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted

as a control signal.

After all data have been transferred, the master generates a STOP condition. A STOP condition is indicated by

pulling SDA from low to high, while SCL is high.

7.5.1.2 Bus Definitions

The TMP451 device is two-wire and SMBus-compatible. Figure 15 and Figure 16 show the timing for various

operations on the TMP451 device. The bus definitions are as follows:

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device

that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup

and hold times into account. On a master receive, data transfer termination can be signaled by the

master generating a not-acknowledge on the last byte that has been transmitted by the slave.

Bus Idle:

Both SDA and SCL lines remain high.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges data transfer.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines

a start condition. Each data transfer initiates with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a

STOP condition. Each data transfer terminates with a repeated START or STOP condition.

(1) Slave address 1001100 shown.

Figure 15. Two-Wire Timing Diagram for Write Word Format

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