TMP512 datasheet(19/62 Pages) TI2

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SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(BUF)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

TMP512

TMP513

www.ti.com

SBOS491A

– JUNE 2010 – REVISED MAY 2011

TIMING DIAGRAMS

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

Figure 28 describes the timing operations on the

limited and is determined by the master device. The

TMP512/13. Parameters for Figure 28 are defined in

receiver acknowledges data transfer.

Table 2. Bus definitions are:

Acknowledge:

Each

receiving

device,

when

Bus Idle: Both SDA and SCL lines remain high.

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

Start Data Transfer: A change in the state of the

SDA line during the Acknowledge clock pulse in such

SDA line, from high to low, while the SCL line is high,

a way that the SDA line is stable low during the high

defines a START condition. Each data transfer

period of the Acknowledge clock pulse. Setup and

initiates with a START condition. Denoted as S in

hold times must be taken into account. On a master

Figure 28.

receive, data transfer termination can be signaled by

Stop Data Transfer: A change in the state of the

the master generating a Not-Acknowledge on the last

SDA line from low to high while the SCL line is high

byte that has been transmitted by the slave.

defines

STOP

condition.

Each

data

transfer

terminates

with

repeated

START

STOP

condition. Denoted as P in Figure 28.

Figure 28. Two-Wire Timing Diagram

Table 2. Timing Characteristics for Figure 28

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

SCL Operating Frequency

f(SCL)

0.001

0.4

0.001

3.4

MHz

Bus Free Time Between STOP and START Condition

t(BUF)

600

160

Hold time after repeated START condition. After this period, the first clock

t(HDSTA)

100

is generated.

Repeated START Condition Setup Time

t(SUSTA)

100

STOP Condition Setup Time

t(SUSTO)

100

Data Hold Time

t(HDDAT)

0(1)

0(2)

Data Setup Time

t(SUDAT)

100

SCL Clock LOW Period

t(LOW)

1300

160

SCL Clock HIGH Period

t(HIGH)

600

Clock/Data Fall Time

300

160

Clock/Data Rise Time

300

160

for SCL

≤ 100kHz

1000

(1)

For cases with fall time of SCL less than 20ns and/or the rise or fall time of SDA less than 20ns, the hold time should be greater than

20ns.

(2)

For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than

10ns.

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