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IS25LE512MG-RGLA2:PTY データシート(PDF) 98 Page - Integrated Silicon Solution, Inc

部品番号 IS25LE512MG-RGLA2:PTY
部品情報  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  194 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE512MG-RGLA2:PTY データシート(HTML) 98 Page - Integrated Silicon Solution, Inc

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IS25LE512MG
IS25WE512MG
Integrated Silicon Solution, Inc.- www.issi.com
98
Rev. A6
10/02/2025
8.18 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.44 Write Disable Sequence In SPI Mode
Instruction = 04h
CE#
SCK
SI
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SO
High Impedance
Figure 8.45 Write Disable Sequence In QPI Mode
04h
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0



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