Data Sheet

ADRF5238

THEORY OF OPERATION

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Rev. 0 | 11 of 13

The ADRF5238 integrates a driver to perform logic functions inter-

nally and to provide the advantage of a simplified CMOS-/LVTTL-

compatible control interface. There are two digital control input pins

(EN and CTRL) that determine which RF port is in the insertion loss

state and in the isolation state. See Table 7 for the control voltage

truth table.

When the EN pin is logic high, all RF paths are in isolation state

regardless of the logic state of the CTRL pin. The RFx ports are

terminated to internal 50Ω resistors, and RFC becomes reflective.

RF INPUT AND OUTPUT

The RF pins (RFC, RF1, and RF2) are DC-coupled, and DC

blocking capacitors are required on the RF lines. The RF ports are

internally matched to 50Ω. Therefore, external matching networks

are not required.

When the EN pin is logic low, the logic level applied to the CTRL

pin determines which RF port is in an insertion loss state and which

RF port is in an isolation state. The insertion loss path conducts the

RF signal between the selected RF throw port and the RF common

port. The isolation path provides high loss between the insertion

loss path and the unselected RF throw port that is terminated to an

internal 50Ω resistor.

When the EN pin is logic high, the switch is in an all off state

regardless of the logic state of the CTRL pin. Both the RF1 to RFC

path and the RF2 to RFC path are in an isolation state. The RF1

and RF2 ports are terminated to internal 50Ω resistors, and the

RFC port becomes reflective open.

The ADRF5238 is bidirectional with equal power handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

POWER SUPPLY

The ADRF5238 requires a positive supply on the VDD pin. Bypass-

ing capacitors are recommended on the supply lines to minimize

RF coupling.

The power-up sequence is as follows:

1. Connect GND.

2. Power up VDD.

3. Apply the digital control inputs. The relative order of the logic

control inputs is not important. Powering the digital control

inputs before VDD can inadvertently forward bias and damage

ESD protection structures. To avoid this damage, use a series

1kΩ resistor to limit the current flowing into the digital control

pins. Use pull-up or pull-down resistors if the controller is in a

high impedance state after VDD is powered up and the control

pins are not driven to a valid logic state.

4. Apply RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 7. Control Voltage Truth Table

CTRL State

EN State

RFC to RF1

RFC to RF2

Low

Low

Off

On

High

Low

On

Off

Low

High

Off

Off

High

High

Off

Off