REF5010AID datasheet(30/52 Pages) TI2

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• Add a high-frequency, 1μF capacitor in parallel between the output and ground to filter noise and help with

switching loads as data converters.

9.4.1.2 REF50xxEI Layout Guidelines

• Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The

recommended value of this bypass capacitor is from 0.1μF to 10μF. If necessary, add decoupling capacitance

to compensate for noisy or high-impedance power supplies. Verify that the smallest capacitor is placed

closest to the device.

• Place a 0.1μF to 1μF class 1 noise filtering capacitor between the NR pin and ground.

• Verify that the output decouples with a 1μF to 100μF low ESR (maximum 1Ω) capacitor.

9.4.2 Layout Example

DNC

TEMP

GND

DNC

OUT

TRIM/NR

Figure 9-3. Layout Example for REF50xxI, REF50xxAI

Figure 9-4. Layout Example for REF50xxEI

9.4.3 Power Dissipation

The REF50xx family is specified to deliver current loads of ±10mA over the specified input voltage range. The

temperature of the device increases according to Equation 6:

TJ = TA + PD × θJA

(6)

where

• TJ = junction temperature (°C)

• TA = ambient temperature (°C)

• PD = power dissipated (W)

• θJA = junction-to-ambient thermal resistance (°C/W)

Establish that the REF50xx junction temperature does not exceed the absolute maximum rating of 150°C.

REF50, REF50E

SBOS410O – JUNE 2007 – REVISED OCTOBER 2025

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REF5010AID データシート(PDF) 30 Page - Texas Instruments