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TUSB2E221 データシート(PDF) 20 Page - Texas Instruments |
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TUSB2E221 データシート(HTML) 20 Page - Texas Instruments |
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20 / 63 page ![]() MIN NOM MAX UNIT tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 4.0 µs (1) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum 6.8 Typical Characteristics TJ1E is for egress direction from eUSB2 to USB and TJ1I is for ingress direction from USB to eUSB2 Figure 6-1. Total Additive Jitter (Typical) TUSB2E221 SNLS757D – JUNE 2024 – REVISED OCTOBER 2025 www.ti.com 20 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TUSB2E221 |
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