TUSB8043AI datasheet(39/62 Pages) TI2

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TUSB8043A

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SLLSF94 – JUNE 2019

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8.5.25 SMBus Device Status and Command Register

Figure 26. Register Offset F8h

Bit No.

Reset State

Table 30. Bit Descriptions – SMBus Device Status and Command Register

Bit

Field

Type

Description

7:2

RSVD

Reserved. Read only, returns 0 when read.

smbusRst

RSU

SMBus interface reset. This bit loads the registers back to their GRSTz

values. Note, that since this bit can only be set when in SMBus mode

the cfgActive bit is also reset to 1. When software sets this bit it must

reconfigure the registers as necessary.

This bit is set by writing a 1 and is cleared by hardware on completion

of the reset. A write of 0 has no effect.

cfgActive

RCU

Configuration active. This bit indicates that configuration of the

TUSB8043A is currently active. The bit is set by hardware when the

device enters the I2C or SMBus mode. The TUSB8043A shall not

connect on the upstream port while this bit is 1.

When in I2C mode, the bit is cleared by hardware when the

TUSB8043A exits the I2C mode.

When in the SMBus mode, this bit must be cleared by the SMBus host

in order to exit the configuration mode and allow the upstream port to

connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

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