L4937NPD datasheet(6/9 Pages) STMICROELECTRONICS

6 / 9 page

Figure 2 : Quiescent Current vs. Supply Voltage.

Figure 3 : Programmable Output 2 Voltage with External Resistors.

400

200

RESET CIRCUIT

The blockcircuit diagramof thereset circuit is shown

in fig.4. The reset circuit supervisesthe standbyout-

put voltage. The reset threshold of 4.7V is defined

by the internal reference voltage and the standby

output divider.

The reset pulse delay time tRD, is defined by the

charge time of an external capacitor CT :

CT x2V

tRD =

µA

The reactiontime of the reset circuit dependson the

discharge time limitation of the reset capacitor CT

and is proportional to the value of CT.

The reaction time of the reset circuit increases the

noise immunity. In fact,if the standbyoutputvoltage

drops below the reset threshold for a time shorter

than the reaction time tRR, no reset output variation

occurs. The nominal reset delay is generated for

standby output voltage drops longer than the time

necessary for the complete discharging of the ca-

pacitor CT. This time is typically equal to 50

µsif

CT = 100nF.The typical reset output waveforms are

shown in fig. 5.

L4937NPD

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L4937NPD データシート(PDF) 6 Page - STMicroelectronics