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ADE7569ASTZF16 データシート(PDF) 97 Page - Analog Devices |
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ADE7569ASTZF16 データシート(HTML) 97 Page - Analog Devices |
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97 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 97 of 144 Table 79. LCD Configuration X SFR (LCDCONX, 0x9C) Bit Mnemonic Default Description 7 Reserved 0 Reserved. External Resistor Ladder Selection Bit. 6 EXTRES 0 EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. 5 to 0 BIASLVL[5:0] 0 Bias Level Selection Bits. See Table 80. Table 80. LCD Bias Voltage When Contrast Control Is Enabled 1/2 Bias 1/3 Bias BIASLVL[5] VA (V) VB VC VB VC [] 31 4:0 BLVL V REF × 0 VB = VA VC = 2 × VA VB = 2 × VA VC = 3 × VA [] ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + × 31 1 4:0 BLVL V REF 1 VC = 2 × VA VB = 2 × VA VC = 3 × VA VB = VA Table 81. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit Mnemonic Default Description 7 Reserved 0 This bit should be kept cleared for proper operation. 6 INV_LVL 0 Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is cleared, frames are not inverted. 5 to 2 Reserved 0 These bits should be kept cleared for proper operation. 1 UPDATEOVER 0 Update Finished Flag Bit. This bit is updated by the LCD driver. When set, this bit indicates that the LCD memory has been updated and a new frame has begun. 0 REFRESH 0 Refresh LCD Data Memory Bit. This bit should be set by the user. When set, the LCD driver does not use the data in the LCD data registers to update the display. The LCD data registers can be updated by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display at the next frame. Table 82. LCD Clock SFR (LCDCLK, 0x96) Bit Mnemonic Default Description Blink Mode Clock Source Configuration Bits. 7 to 6 BLKMOD[1:0] 0 BLKMOD[1:0] Result 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 10 The blink rate is 2 Hz. 11 The blink rate is set by BLKFREQ[1:0]. Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11. 5 to 4 BLKFREQ[1:0] 0 BLKFREQ[1:0] Result (Blink Rate) 00 1 Hz 01 1/2 Hz 10 1/3 Hz 11 1/4 Hz 3 to 0 FD[3:0] 0 LCD Frame Rate Selection Bits. See Table 83 and Table 84. |
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