25CS160-ESLASHQ4B datasheet(16/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 16

25CS160

4.4

Hold Function

The HOLD pin is used to pause the serial

communication with the device without having to stop

or reset the clock sequence. Hold mode, however,

does not affect the internal write cycle. Therefore, if a

write cycle is in progress, asserting the HOLD pin will

not pause the operation, and the write cycle will

continue until it is finished.

Hold mode can only be entered while the CS pin is

asserted. Hold mode is activated by asserting the

HOLD pin during the SCK low pulse. If the HOLD pin is

asserted during the SCK high pulse, then Hold mode

will not start until the beginning of the next SCK low

pulse. The device will remain in Hold mode as long as

the HOLD and CS pins are asserted.

While in Hold mode, the SO pin will be in a

high-impedance state. In addition, both the SI pin and

the SCK pin will be ignored. The WP pin, however, can

still be asserted or deasserted while in Hold mode.

To end Hold mode and resume serial communication,

the HOLD pin must be deasserted during the SCK low

pulse. If the HOLD pin is deasserted during the SCK

high pulse, then Hold mode will not end until the

beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still

asserted, then any sequence that may have been

started will be aborted.

FIGURE 4-2:

HOLD MODE

4.5

Write Protection

The EEPROM array can only be programmed in

accordance with how the Block Protect bits in the

STATUS

are

programmed.

Refer

Section 6.1.2 “Block Write-Protect Bits” for details.

Additionally, the contents of the STATUS register can

be protected by enabling the Write-Protect Enable

(WPEN) bit in the STATUS register.

When the WPEN function is enabled, the STATUS

asserted (low). Details about the WPEN function are

provided in Section 6.1.1 “Write-Protect Enable Bit”.

HOLD

Hold

SCK

Hold

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