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ISL91211AIIZ-T データシート(PDF) 9 Page - Renesas Technology Corp |
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ISL91211AIIZ-T データシート(HTML) 9 Page - Renesas Technology Corp |
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9 / 57 page  FN8922 Rev.3.01 Page 9 of 56 Mar 5, 2020 ISL91211A, ISL91211B 1.6 I/O Pin Configuration The ISL91211 features three “General Purpose” I/O pins for I2C and other functions along with four “Multipurpose” I/O pins. These pins can perform different functions depending on the “IO_PINMODE” setting. The default factory setting for IO_PINMODE is 0x0. For features that require “IO_PINMODE” to be different than the default value, contact Renesas for factory OTP programming. Table 2. I/O Pin Mode IO_PINMODE MPIO0 MPIO1 MPIO2 MPIO3 GPIO0 GPIO1 GPIO2 Description 0x0 SCK SS_B MOSI MISO I2C_CLK I2C_SDA N/A I2C/SPI both available 0x1 SCK SS_B MOSI MISO EN_A EN_B EN_C SPI mode with hardware enables for Bucks 1-3 0x2 PGOOD1 PGOOD2 PGOOD3 PGOOD4 I2C_CLK I2C_SDA N/A I2C with Individual PGOODs for Bucks1-4 0x3 SCK SS_B MOSI MISO DVS_A DVS_B DVS_C SPI with hardware DVS pins 0x4 DVS_PIN1 DVS_PIN0 PGOOD1 PGOOD2 I2C_CLK I2C_SDA N/A I2C with Global DVS mode with PGOOD1 and PGOOD2 0x5 BUCK1_DVS0 BUCK1_DVS1 BUCK2_ DVS0 BUCK2_ DVS1 I2C_CLK I2C_SDA N/A I2C with full pin controlled DVS for BUCK1/BUCK2 0x6 BUCK1_DVS0 BUCK1_DVS1 BUCK2_ DVS0 BUCK3_ DVS0 I2C_CLK I2C_SDA N/A I2C with full DVS for Buck 1, 1-pin DVS for BUCK2/BUCK3 0x7 BUCK1_DVS0 BUCK2_DVS0 BUCK3_ DVS0 BUCK4_ DVS0 I2C_CLK I2C_SDA N/A I2C with 1-pin DVS for each buck 0xC MPIO_DATA [0] MPIO_DATA [1] MPIO_ DATA [2] MPIO_ DATA [3] I2C_CLK I2C_SDA N/A I2C with 4 parallel controllable data lines. NOTE: Pinmodes 0x8 through 0xB and 0xD through 0xF are reserved. Table 3. Pin Mode Description Name Definition SCK SPI clock SS_B SPI/I2C selector. Low = SPI, High = I2C. MOSI SPI master out, slave in MISO SPI master in, slave out I2C_CLK I2C clock I2C_SDA I2C data PGOOD1, PGOOD2, PGOOD3, PGOOD4 Four power-good out pins (one per buck) EN_A, EN_B, EN_C Three buck enable input pins. A single buck enable pin can enable/disable up to four bucks. A buck’s enable/disable can be controlled from only one enable pin (EN_A, EN_B, or EN_C). DVS_A, DVS_B, DVS_C Three DVS input pins. A single DVS pin can control the DVS voltage for up to four bucks. A buck’s DVS voltage can be controlled from only one DVS pin (DVS_A, DVS_B, or DVS_C). DVS_PIN1, DVS_PIN0 DVS look-up table to allow two pins to control up to four bucks. |
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