IS25LP016D-RMLA3 datasheet(24/115 Pages) ISSI

部品番号	IS25LP016D-RMLA3

部品情報	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	115 Pages

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メーカー	ISSI [Integrated Silicon Solution, Inc]

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IS25LP016D

IS25WP016D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B16

01/01/2025

7. PROTECTION MODE

The device supports hardware and software write-protection mechanisms.

7.1 HARDWARE WRITE PROTECTION

The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and

QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.

Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will

be ignored when Vcc drops to VWI.

Table 7.1 Hardware Write Protection on Status Register

SRWD

WP#

Status Register

Low

Writable

Low

Protected

High

Writable

High

Writable

Note: Before the execution of any program, erase or write Status Register instruction, the Write Enable Latch (WEL)

bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program,

erase or write register instruction will be ignored.

7.2 SOFTWARE WRITE PROTECTION

The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, BP0) bits allow

part or the whole memory area to be write-protected.

IS25LP016D-RMLA3 データシート(PDF) 24 Page - Integrated Silicon Solution, Inc