L6615 datasheet(16/20 Pages) STMICROELECTRONICS

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L6615

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Consider, for example an application with VOUT = 1.2V and the sense resistor placed high side; the voltage

at CS+:

VCS+ = VOUT - ∆VSENSE

is lower than 1.6V so the internal comparator triggers on the LSA structure and the pin CS- sources the

current ICS (see paragraph "2. CURRENT SENSE SECTION"). The IC works properly because the dy-

namics of LSA spreads down to zero: in this case it is necessary to pay attention to the design of ADJ

network.

Now consider, for example, an application with VOUT =1.5V where, because of the drop across RSNS, the

voltage at CS+ pin could be very close to the threshold: if such voltage is overcome (start-up, load regu-

lation, overvoltage,…) , then the HSA structure will be activated; as nominal conditions are restored, the

hysteresis will then keep HSA active (unless VCS+ falls under the lower threshold).

OFFSET TRIMMING

The current sharing accuracy strongly depends on the unbalance between the relevant parameters of the

paralleled sections. Each percentage point on the relevant parameters tolerance introduces a maximum

error equal to the double of the tolerance.The L6615 introduces an inherent error in current sharing due

to the 40mV offset at the negative input of the error amplifier; this offset is necessary to guarantee the low

value of the master COMP pin.

Considering perfectly matched all other parameters, the offset introduces a percentage error equal to 4%

divided by the voltage on the share bus. In particular:

Being VSH directly proportional to the load current and fixed the ratio RCGA/RG, higher are the currents

involved in the sharing, lower is the error.

Another error is introduced by the current sense amplifier due to its input offset whose amplitude can be

±1mV: being typically the drop across RSNS about one hundred mV at full load, the offset could lead to an

error of some percentage point.

Whenever the application requires very high current sharing accuracy, it is possible to correct these offsets

through a triggering process, introducing a trimmer (RK) between current sense input pins.

Referring to fig. 16, in case of high side sensing, the equations governing the circuit are:

VP = VM + VO

where VO is the current sense amplifier input offset.

Solving for IG, we get:

Ideally IG should be equal only to the first term: this current will be sunk by CS+ pin, internally mirrored

with 1:1 ratio and sent to CGA pin.

Imposing that the sum of two latter terms is zero it is possible to find the value of

δ deleting the effect of

the offset:

SLAV E

MAST ER

40m A

----------------

–





⋅

OUT

–

-----------------------------

–

() R

⋅

-----------------------------

OUT

SENSE

–

---------------------------------------------------------

δ R

⋅

---------------

–

SENSE

----------------------

δ R

⋅

δ R

⋅⋅

------------------------------ V

OUT

δ 1

–

⋅

δ R

–

() R

⋅

[]

⋅

--------------------------------------------------------

⋅

–

OPT

---

OUT

⋅⋅

⋅

⋅⋅

–

⋅⋅

------------------------------------------------------------------------------------------------------------------------------------------------------------

–

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