CY7C63001A
CY7C63101A
Document #: 38-08026 Rev. *A
Page 9 of 25
Each GPIO line includes an internal Rup resistor. This resistor
provides both the pull-up function and slew control. Two
factors govern the enabling and disabling of each resistor: the
state of its associated Port Pull-up register bit and the state of
the Data Register bit. NOTE: The control bits in the Port Pull-
up register are active LOW.
A GPIO line is HIGH when a “1” is written to the Data Register
and a “0” is written to the respective Port Pull-up register.
Writing a “0” to the port Data Register disables the port’s Pull-
up resistor and outputs a LOW on the GPIO line regardless of
the setting in the Port Pull-up Register. The output goes to a
high-Z state if the Data Register bit and the Port Pull-up
Register bit are both “1”. Figure 6-10 illustrates the block
diagram of one I/O line. The Port Isink Register is used to
control the output current level and it is described later in this
section. NOTE: The Isink logic block is turned off during
suspend mode (please refer to the Instant-on Feature section
for more details). Therefore, to prevent higher ICC currents
during USB suspend mode, firmware must set ALL Port 0 and
Port 1 Data Register bits (which are not externally driven to a
known state), including those that are not bonded out on a
particular package, to “1” and all Port 0 and Port 1 Pull-Up
Register data bits to “0” to enable port pull-ups before setting
the Suspend bit (bit 3 of the Status and Control Register).
Table 6-2 is the Output Control truth table.
To configure a GPIO pin as an input, a “1” should be written to
the Port Data Register bit associated with that pin to disable
the pull-down function of the Isink DAC (see Figure 6-
10).When the Port Data Register is read, the bit value is a “1”
if the voltage on the pin is greater than the Schmitt trigger
threshold, or “0” if it is below the threshold. In applications
where an internal pull-up is required, the Rup pull-up resistor
can be engaged by writing a “0” to the appropriate bit in the
Port Pull-up Register.
Both Port 0 and Port 1 Pull-up Registers are write only (see
Figures 6-11 and 6-12). The Port 0 Pull-up Register is located
at I/O address 0x08 and Port 1 Pull-up Register is mapped to
address 0x09. The contents of the Port Pull-up Registers are
cleared during reset, allowing the outputs to be controlled by
the state of the Data Registers. The Port Pull-up Registers also
select the polarity of transition that generates a GPIO interrupt.
A “0” selects a HIGH to LOW transition while a “1” selects a
LOW to HIGH transition.
Figure 6-10. Block Diagram of an I/O Line
Table 6-2. Output Control Truth Table
Data Register
Port Pull-up Register
Output at I/O Pin
Interrupt Polarity
0
0
Sink Current (‘0’)
High to Low
0
1
Sink Current (‘0’)
Low to High
1
0
Pull-up Resistor (‘1’)
High to Low
1
1
Hi-Z
Low to High
GPIO
Pin
VCC
Isink
DAC
Port Isink
Register
Port Data
Register
Port Pull-Up
Register
Rup
Data Bus
Schmitt
Trigger
Suspend
Bit
Disable
b7
b6
b5
b4
b3
b2
b1
b0
PULL0.7
PULL0.6
PULL0.5
PULL0.4
PULL0.3
PULL0.2
PULL0.1
PULL0.0
WW
WW
WW
W
W
00
00
000
0
Figure 6-11. Port 0 Pull-up Register (Address 0x08)
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