CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *B
Page 9 of 19
Bank Select Pipelined Read[21, 22]
Left Port Write to Flow-Through Right Port Read[23, 24, 25, 26]
Notes:
21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
22. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
23. The same waveforms apply for a right port write to flow-through left port read.
24. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
25. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
26. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
D3
D1
D0
D2
A0
A1
A2
A3
A4
A5
D4
A0
A1
A2
A3
A4
A5
tSA
tHA
tSC
tHC
tSA
tHA
tSC
tHC
tSC
tHC
tSC tHC
tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2
tCD2
tCKHZ
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCH2
tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
tSA
tHA
tSW
tHW
tSD
tHD
MATCH
VALID
tCCS
tSW
tHW
tDC
tCWDD
tCD1
MATCH
tSA
tHA
MATCH
NO
MATCH
NO
VALID
VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
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