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CY2310ANZPVC-1 データシート(PDF) 2 Page - Cypress Semiconductor

部品番号 CY2310ANZPVC-1
部品情報  3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
PDF  8 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2310ANZPVC-1 データシート(HTML) 2 Page - Cypress Semiconductor

  CY2310ANZPVC-1 Datasheet HTML 1Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 2Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 3Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 4Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 5Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 6Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 7Page - Cypress Semiconductor CY2310ANZPVC-1 Datasheet HTML 8Page - Cypress Semiconductor  
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CY2310ANZ
Document #: 38-07142 Rev. *B
Page 2 of 8
Device Functionality
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• Serial interface address for the CY2310ANZ is:
Pin Summary
Name
Pins
Description
VDD
1, 5, 10, 19, 24, 28
3.3V Digital voltage supply
VSS
4, 8, 12, 17, 21, 25
Ground
VDDIIC
13
Serial interface voltage supply
VSSIIC
16
Ground for serial interface
BUF_IN
9
Input clock
OE
20
Output Enable, three-states outputs when LOW. Internal pull-up to VDD
SDATA
14
Serial data input, internal pull-up to VDD
SCLK
15
Serial clock input, internal pull-up to VDD
SDRAM [0–3]
2, 3, 6, 7
SDRAM byte 0 clock outputs
SDRAM [4–7]
22, 23, 26, 27
SDRAM byte 1 clock outputs
SDRAM [8–9]
11, 18
SDRAM byte 2 clock outputs
OE
SDRAM [0–17]
0
High-Z
1
1 x BUF_IN
A6
A5
A4
A3
A2
A1
A0
R/W
1101001
----
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enabled
Bit
Pin #
Description
Bit 7 --
Initialize to 0
Bit 6 --
Initialize to 0
Bit 5 --
Initialize to 0
Bit 4 --
Initialize to 0
Bit 3 7
SDRAM3 (Active/Inactive)
Bit 2 6
SDRAM2 (Active/Inactive)
Bit 1 3
SDRAM1 (Active/Inactive)
Bit 0 2
SDRAM0 (Active/Inactive)
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
27
SDRAM7 (Active/Inactive)
Bit 6
26
SDRAM6 (Active/Inactive)
Bit 5
23
SDRAM5 (Active/Inactive)
Bit 4
22
SDRAM4 (Active/Inactive)
Bit 3
--
Initialize to 0
Bit 2
--
Initialize to 0
Bit 1
--
Initialize to 0
Bit 0
--
Initialize to 0
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
18
SDRAM9 (Active/Inactive)
Bit 6
11
SDRAM8 (Active/Inactive)
Bit 5
--
Reserved, drive to 0
Bit 4
--
Reserved, drive to 0
Bit 3
--
Reserved, drive to 0
Bit 2
--
Reserved, drive to 0
Bit 1
--
Reserved, drive to 0
Bit 0
--
Reserved, drive to 0



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