TAS5706PAP datasheet(43/62 Pages) TI

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CLOCK CONTROL REGISTER (0x00)

DEVICE ID REGISTER (0x01)

TAS5706

SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007

In the manual mode, the clock control register provides a way for the system microprocessor to update the data

and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks

are automatically determined by the TAS5706. In this case, the clock control register contains the auto-detected

clock status as automatically detected (D7–D2). Bits D7–D5 selects the sample rate. Bits D4–D2 select the

MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be

written to D0 to inform the DAP that the written clocks are valid.

Table 3. Clock Control Register (0x00)

FUNCTION

–

fS = 32-kHz sample rate

–

fS = 38-kHz sample rate

–

fS = 44.1-kHz sample rate

–

fS = 48-kHz sample rate

(1)

–

fS = 88.2-kHz sample rate

–

fS = 96-kHz sample rate

–

fS = 176.4-kHz sample rate

–

fS = 192-kHz sample rate

–

MCLK frequency = 64

× f

(2)

–

MCLK frequency = 128

× f

(3)

–

MCLK frequency = 192

× f

–

MCLK frequency = 256

× f

(1)

–

MCLK frequency = 384

× f

(4)

–

MCLK frequency = 512

× f

(4)

–

Reserved

–

Reserved

–

Bit clock (SCLK) frequency = 48

× f

(5)

Bit clock (SCLK) frequency = 64

× f

S or 32 × fS (selected in register

–

0x04) (1)

–

Clock not valid (in manual mode only) (1)

–

Clock valid (in manual mode only)

(1)

Default values are in bold.

(2)

Rate not available for 32-, 44.1-, and 48-kHz data rates

(3)

Rate not available for 32-kHz data rate

(4)

Rate not available for 176.4-kHz and 192-kHz data rates

(5)

Rate only available for 192-fS and 384-fS MCLK frequencies

The device ID register contains the ID code for the firmware revision.

Table 4. General Status Register (0x01)

FUNCTION

–

Default (1)

–

Identification code

(1)

Default values are in bold.

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