TAS5706PAPRG4 datasheet(26/62 Pages) TI

部品番号	TAS5706PAPRG4

部品情報	20-W Stereo Digital Audio Power Amplifier with EQ and DRC

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メーカー	TI [Texas Instruments]

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Left-Justified

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelLeft-JustifiedStereoInput

T0034-02

MSB

LSB

SCLK

TAS5706

SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

48, or 64

× f

S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK

toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data bit positions.

NOTE: All data presented in 2s-complement form with MSB first.

Figure 33. Left-Justified 64-fS Format

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TAS5706PAPRG4 データシート(PDF) 26 Page - Texas Instruments