M95256-R datasheet(11/43 Pages) STMICROELECTRONICS

11 / 43 page

M95256, M95256-W, M95256-R

Operating features

11/43

●

deselected (at next power-up, a falling edge is required on Chip Select (S) before any

instruction can be started).

●

not in the Hold condition

●

Status register:

–

the Write Enable Latch (WEL) is reset to 0

–

the Write In Progress (WIP) is reset to 0

–

the SRWD, BP1 and BP0 bits of the Status Register are non-volatile bits and

therefore remain unchanged)

Note:

When VCC passes the power on reset threshold voltage and until it reaches the minimum

VCC operating voltage, the memory must not be selected/accessed.

3.8.4

Power-down

During power-down (continuous decrease in VCC below the minimum VCC operating

voltage), the device must be:

●

deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC)

●

in Standby Power mode (there should not be any internal Write cycle in progress).

Operating features

4.1

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 4).

The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 4 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

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