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M48Z09 データシート(PDF) 2 Page - STMicroelectronics |
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M48Z09 データシート(HTML) 2 Page - STMicroelectronics |
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2 / 13 page ![]() Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 °C TSTG Storage Temperature (VCC Off) –40 to 85 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. Table 2. Absolute Maximum Ratings Mode VCC E1 E2 G W DQ0-DQ7 Power Deselect 4.75V to 5.5V or 4.5V to 5.5V VIH X X X High Z Standby Deselect X VIL X X High Z Standby Write VIL VIH XVIL DIN Active Read VIL VIH VIL VIH DOUT Active Read VIL VIH VIH VIH High Z Active Deselect VSO to VPFD (min) X X X X High Z CMOS Standby Deselect ≤ VSO X X X X High Z Battery Back-up Mode Note: X = VIH or VIL Table 3. Operating Modes A1 A0 DQ0 A7 A4 A3 A2 A6 A5 E2 A10 A8 A9 DQ7 W A11 G E1 DQ5 DQ1 DQ2 DQ3 VSS DQ4 DQ6 A12 INT VCC AI01185 M48Z09 M49Z19 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2A. DIP Pin Connections The M48Z09,19 button cell has sufficient capacity and storage life to maintain data for an accumu- lated time period of at least 11 years in the absence of power over the operating temperature range. The M48Z09,19 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z09,19 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system opera- tion brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns. DESCRIPTION (cont’d) 2/13 M48Z09, M48Z19 |
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