M50FW016 datasheet(13/45 Pages) STMICROELECTRONICS

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M50FW016

Table 4. FWH Bus Read Field Definitions

Note: 1. Clock Cycle Number = (2MSIZE –1)* 2+18

2. Clock Cycle Number = (2MSIZE –1)* 2+19

Figure 5. FWH Bus Read Waveforms (Single Byte Read)

Clock

Cycle

Number

Clock

Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

START

1101b

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Read cycle.

IDSEL

XXXX

Indicates which FWH Flash Memory is selected. The value

on FWH0-FWH3 is compared to the IDSEL strapping on the

FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

3-9

ADDR

XXXX

A 28-bit address phase is transferred starting with the most

significant nibble first. For the multi-byte read operation, the

least significant bits (MSIZE of them) are treated as Don't

Care, and the read operation is started with each of these

bits reset to 0.

MSIZE

0XXXb

This one clock cycle is driven by the host to determine how

many bytes will be transferred. M50FW016 will support:

single byte transfer (0000b), 4-byte transfer (0010b), 16-byte

transfer (0100b) and 128-byte transfer (0111b).

TAR

1111b

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

TAR

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

13-14

WSYNC

0101b

The FWH Flash Memory drives FWH0-FWH3 to 0101b

(short wait-sync) for two clock cycles, indicating that the data

is not yet available. Two wait-states are always included.

RSYNC

0000b

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating that data will be available during the next clock

cycle.

16-17

DATA

XXXX

Data transfer is two CLK cycles, starting with the least

significant nibble.

If multi-byte read operation is

enabled, repeat cycle 16-17 n times, where n = 2MSIZE –1

Note 1

TAR

1111b

The FWH Flash Memory drives FWH0-FWH3 to 1111b to

indicate a turnaround cycle.

Note 2

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs, the host takes

control of FWH0-FWH3.

AI03437

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

IDSEL

ADDR

MSIZE

TAR

SYNC

DATA

TAR

11712322

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