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M50LPW002K データシート(PDF) 5 Page - STMicroelectronics |
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M50LPW002K データシート(HTML) 5 Page - STMicroelectronics |
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5 / 39 page  5/39 M50LPW002 Figure 3. Logic Diagram (LPC Interface) Table 1. Signal Names (LPC Interface) Figure 4. Logic Diagram (A/A Mux Interface) Table 2. Signal Names (A/A Mux Interface) LAD0-LAD3 Input/Output Communications LFRAME Input Communication Frame ID0-ID3 Identification Inputs GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP Interface Reset INIT CPU Reset CLK Clock TBL Top Block Lock WP Write Protect RFU Reserved for Future Use. Leave disconnected VCC Supply Voltage VPP Optional Supply Voltage for Fast Erase Operations VSS Ground NC Not Connected Internally AI05742 4 LFRAME LAD0- LAD3 VCC M50LPW002 CLK VSS 4 IC RP TBL 5 INIT WP ID0-ID3 GPI0- GPI4 VPP IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RB Ready/Busy Output RP Interface Reset VCC Supply Voltage VPP Optional Supply Voltage for Fast Program and Fast Erase Operations VSS Ground NC Not Connected Internally AI05743 11 RC DQ0-DQ7 VCC M50LPW002 IC VSS 8 G W RB RP A0-A10 VPP |
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