M54HC259

M74HC259

October 1992

8 BIT ADDRESSABLE LATCH

B1R

(Plastic Package)

ORDER CODES :

M54HC259F1R

M74HC259M1R

M74HC259B1R

M74HC259C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL PROPAGATION DELAYS

.

BALANCED PRORAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS259

DESCRIPTION

The M54/74HC259 is a high speed CMOS 8 BIT

ADDRESSABLE LATCH fabricated in silicon gate

C

formance of LSTTL combined with true CMOS low

power consumption.

The M54HC259/M74HC259 has single data input

(D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B,

and C), common enable input (E), and a common

CLEAR input. To operate this device as an address-

able latch, data is held on the D input, and the ad-

dress of the latch into which the data is to be entered

is held on the A, B, and C inputs. When ENABLE is

taken low the data flows through to the addresses

output. The data is stored on the positive-going

edge of the ENABLE pulse. All unaddressed latches

will remain unaffected. With ENABLE in the high

state the device is deselected and all latches remain

in their previous state, unaffected by changes on the

data or address inputs. To eliminate the possibility

of entering erroneous data into the latches, the EN-

ABLE should be held high (inactive) while the ad-

dress lines are changing. If ENABLE is held high and

CLEAR is taken low all eight latches are cleared to

the low state. If ENABLE is low all latches except the

addressed latch will be cleared. The addressed

latch will instead follow the D input, effectively imple-

menting a 3-to 8 line decoder.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

1/12