USBDFXXW5_06 datasheet(5/11 Pages) STMICROELECTRONICS

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USBDFxxW5

Application information

5/11

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give

the typical dynamical resistance value Rd. Taking into account the following hypothesis:

Rt > Rd, Rg > R and Rload > Rd, gives these formulas::

The results of the calculation done for VPP = 8 kV, Rg = 330 W (IEC61000-4-2 standard),

VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also

important to note that in this approximation the parasitic inductance effect was not taken into

account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect

is not present at the Vout side due the low current involved after the resistance R.

The measurements results shown below show very clearly (Figure 7.) the high efficiency of

the ESD protection :

●

no influence of the parasitic inductances on Vout stage

●

output clamping voltage very close to VBR (positive strike) and -VF (negative strike)

Figure 6.

Measurement board

input

output

R.V

+ R. V

gBR

R.V

+ R . V

input

TEST BOARD

ESD

SURGE

15 kV

Air

Discharge

Vin

Vout

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