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M74HC73 データシート(PDF) 1 Page - STMicroelectronics |
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M74HC73 データシート(HTML) 1 Page - STMicroelectronics |
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1 / 11 page ![]() 1/11 August 2001 s HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 73 DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HC73B1R SOP M74HC73M1R M74HC73RM13TR TSSOP M74HC73TTR TSSOP DIP SOP |
同様の部品番号 - M74HC73 |
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同様の説明 - M74HC73 |
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