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AS3722 データシート(PDF) 149 Page - ams-OSRAM AG |
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AS3722 データシート(HTML) 149 Page - ams-OSRAM AG |
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149 / 199 page  Page 148 ams Datasheet Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 164: CTRLsequ1 Addr:58h CTRLsequ1 Bit Bit Name Default Access Bit Description 0 ac_ok_pwr_on 0 RW_SS Enables exit out of PWR OFF mode with pin AC_OK (pin enabled in PWR off mode) 0 : AC_OK disabled 1 : AC_OK enabled 1 lid_pwr_on 0 RW_SS Enables exit out of PWR OFF mode with pin LID (pin enabled in PWR off mode) 0 : LID disabled 1 : LID enabled 2therm_inv 0 RW_SS Sets the polarity of the THERM pin 0 : High active for THERM event 1 : Inverted: Low active for THERM event 3enable2_inv 0 RW_SS Sets the polarity of the ENABLE2 pin 0 : High active for ENALBE2 1 : Inverted: Low active for ENABLE2 4 enable1_inv 0 RW Sets the polarity of the ENABLE1 pin 0 : High active for ENABLE1 1 : Inverted: Low active for ENABLE1 5 enable1_deepsleep 0 RW ENABLE1 signal enable for controlling deepsleep/stand_by 0 : ENABLE1 signal not used for stand_by entry/exit 1 : ENABLE1 signal used for stand_by entry/exit 6 onkey_nodebounce 0 RW Sets the debounce on ONKEY 0 : debounce on 1 : debounce off 7enable3_inv 0 RW_SS Sets the polarity of the ENABLE3 pin 0 : High active for ENABLE3 1 : Inverted: Low active for ENABLE3 |
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