AS7331-AQFM datasheet(39/72 Pages) AMSOSRAM

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AS7331

Functional Description

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 38

64x

10.13

5.07

2.53

1.27

0.63

0.32

0.16

2593.75

32x

20.26

10.13

5.07

2.53

1.27

0.63

0.32

5187.50

16x

40.53

20.26

10.13

5.07

2.53

1.27

0.63

10375.00

81.05

40.53

20.26

10.13

5.07

2.53

1.27

20750.00

162.11

81.05

40.53

20.26

10.13

5.07

2.53

41500.00

324.22

162.11

81.05

40.53

20.26

10.13

5.07

83000.00

648.44

324.22

162.11

81.05

40.53

20.26

10.13

166000.00

(1)

TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV,

RESOL

– Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given

by CREG1:GAIN = 0 dec (see Figure 48).

In the SYND mode, the maximum value of the conversion result depends on the externally controlled

conversion time. This maximum achievable count is equal to OUTCONV and differs from the full-scale

count achievable in CMD, CONT, and SYNS modes.

The value of CREG1:TIME defines the number of clock counts during the conversion time. It defines

the conversion time duration and maximal resolution of the A/D conversion. This is valid for the CONT,

CMD, and SYNS modes.

In the SYND mode, the value of CREG1:TIME does not have any meaning for the conversion time

duration, because this time is externally defined.

For values of CREG1:TIME higher than 6 dec (0110b), TCONV becomes bigger than 216, which results

in A/D conversions with a higher resolution starting from 17-bit up to 24-bit. Only the least 16

significant bits are further processed and stored in the result registers. Using the implemented divider

(see chapter 7.5) helps to access the upper 8-bits, too.

The value of CREG1:GAIN defines the A/D converter’s gain (see Figure 48 and the FSR values in

Figure 27 to Figure 32

), which determines the sensor’s irradiance responsivity Re. The values of

CREG1:GAIN, of the referred tables, are only valid for a clock frequency fCLK, of 1 MHz. For higher

clock frequencies, some gain increments are not accessible. Figure 33 shows the valid gains

dependent on the chosen internal system clock via CREG3:CCLK.

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