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M95256 データシート(PDF) 20 Page - STMicroelectronics

部品番号 M95256
部品情報  256 Kbit Serial SPI bus EEPROM with high speed clock
PDF  39 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95256 データシート(HTML) 20 Page - STMicroelectronics

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POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
–
Standby Power mode
–
deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
–
not in the Hold Condition
–
the Write Enable Latch (WEL) is reset to 0
–
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Initial Delivery State
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.



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