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STA015T データシート(PDF) 29 Page - STMicroelectronics |
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STA015T データシート(HTML) 29 Page - STMicroelectronics |
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29 / 55 page  29/55 STA015 STA015B STA015T If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is neverthe- less affected with the value 0x01 if a discrepance has occurred. MFSDF_441 Address: 0x50 (80) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register contains the value for the PLL X driver for the 44.1KHz reference frequency. The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 (81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ADPCM_DATA_READY Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ADR: Adpcm Data Ready This bit signal ADPCM encoded data are ready to be retrieved. PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X M4M3M2M1M0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XX XXXXX ADR |
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