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24FC08-E/ST データシート(PDF) 4 Page - Microchip Technology |
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24FC08-E/ST データシート(HTML) 4 Page - Microchip Technology |
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4 / 49 page  24AA08/24LC08B/24FC08 DS20001710N-page 4 2002-2021 Microchip Technology Inc. TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC08B) Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC08) Param. No. Symbol Characteristic Min. Max. Units Conditions 1FCLK Clock Frequency — 400 kHz 2.5V ≤ VCC ≤ 5.5V — 100 kHz 1.7V ≤ VCC <2.5V (24AA08) — 1000 kHz 1.7V ≤ VCC ≤ 5.5V (24FC08) 2THIGH Clock High Time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — ns 1.7V ≤ VCC <2.5V (24AA08) 260 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 3TLOW Clock Low Time 1300 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — ns 1.7V ≤ VCC <2.5V (24AA08) 500 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 4TR SDA and SCL Rise Time — 300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) — 1000 ns 1.7V ≤ VCC <2.5V (24AA08) (Note 1) — 1000 ns 1.7V ≤ VCC ≤ 5.5V (24FC08) (Note 1) 5TF SDA and SCL Fall Time — 300 ns Note 1 6THD:STA Start Condition Hold Time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — ns 1.7V ≤ VCC <2.5V (24AA08) 250 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 7TSU:STA Start Condition Setup Time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — ns 1.7V ≤ VCC <2.5V (24AA08) 250 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 8THD:DAT Data Input Hold Time 0 — ns Note 2 9TSU:DAT Data Input Setup Time 100 — ns 2.5V ≤ VCC ≤ 5.5V 250 — ns 1.7V ≤ VCC <2.5V (24AA08) 50 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 10 TSU:STO Stop Condition Setup Time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — ns 1.7V ≤ VCC <2.5V (24AA08) 250 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 11 TSU:WP WP Setup Time 600 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 12 THD:WP WP Hold Time 600 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) 13 TAA Output Valid from Clock — 900 ns 2.5V ≤ VCC ≤ 5.5V (Note 2) — 3500 ns 1.7V ≤ VCC <2.5V (24AA08) (Note 2) — 450 ns 1.7V ≤ VCC ≤ 5.5V (24FC08) (Note 2) 14 TBUF Bus Free Time: The time the bus must be free before a new transmission can start 1300 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — ns 1.7V ≤ VCC <2.5V (24AA08) 500 — ns 1.7V ≤ VCC ≤ 5.5V (24FC08) Note 1: Characterized but not 100% tested. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: CB = total capacitance of one bus line in pF. 4: This parameter is not tested but ensured by characterization. |
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