PSD913F2 datasheet(63/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.5.3 Reset and Power On Requirement

9.5.3.1 Power On Reset

Upon power up the PSD9XX requires a reset pulse of tNLNH-PO (minimum 1 ms) after

VCC is steady. During this time period the device loads internal configurations, clears

some of the registers and sets the Flash into operating mode. After the rising edge of

reset, the PSD9XX remains in the reset state for an additional tOPR (maximum 120 ns)

nanoseconds before the first memory access is allowed.

The PSD9XX Flash memory is reset to the read array mode upon power up. The FSi

and CSBOOTi select signals along with the write strobe signal must be in the false

state during power-up reset for maximum security of the data contents and to remove

the possibility of a byte being written on the first edge of a write strobe signal. Any Flash

memory write cycle initiation is prevented automatically when VCC is below VLKO.

9.5.3.2 Warm Reset

Once the device is up and running, the device can be reset with a much shorter pulse of

tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational

after warm reset. Figure 25 shows the timing of the power on and warm reset.

OPERATING LEVEL

POWER ON RESET

VCC

RESET

t NLNH–PO

t OPR

t NLNH-A

t NLNH

t OPR

WARM

RESET

Figure 25. Power On and Warm Reset Timing

9.5.3.3

I/O Pin, Register and PLD Status at Reset

Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset

and power down mode. PLD outputs are always valid during warm reset, and they are

valid in power on reset once the internal PSD configuration bits are loaded. This loading of

PSD is completed typically long before the VCC ramps up to operating level. Once the PLD

is active, the state of the outputs are determined by the PLD equations.

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