MPC852T datasheet(3/80 Pages) FREESCALE

3 / 80 page

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

Features

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory

devices

— DRAM controller-programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes–256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

•

Fast Ethernet controller (FEC)

•

General-purpose timers

— Two 16-bit timers or one 32-bit timer

— Gate mode can enable or disable counting

— Interrupt can be masked on reference match and event capture

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1™ standard test access port (JTAG)

•

Interrupts

— Seven external interrupt request (IRQ) lines

— Seven port pins with interrupt capability

— Eighteen internal interrupt sources

— Programmable priority between SCCs

— Programmable highest-priority request

•

Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE

, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Eight serial DMA (SDMA) channels

— Three parallel I/O registers with open-drain capability

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