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ADRF5715BCCZN-R7 データシート(PDF) 13 Page - Analog Devices |
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ADRF5715BCCZN-R7 データシート(HTML) 13 Page - Analog Devices |
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13 / 14 page ![]() Data Sheet ADRF5715 APPLICATIONS INFORMATION analog.com Rev. 0 | 13 of 14 The RF transmission lines are designed using a coplanar wave- guide (CPWG) model with a trace width of 16 mil and ground clearance of 6 mil to have a characteristic impedance of 50 Ω. For optimal RF and thermal grounding, as many through vias as possible are arranged around transmission lines and under the exposed pad of the package. The RF input and output ports (ATTIN and ATTOUT) are connected through 50 Ω transmission lines. On the VDD and VSS supply traces, a 100 pF bypass capacitor filters high frequency noise. Figure 20 shows the simplified application circuit for the ADRF5715. Figure 20. Simplified Application Circuit RECOMMENDATIONS FOR PCB DESIGN The RF ports are matched to 50 Ω internally, and the pinout is designed to mate a CPWG with a 50 Ω characteristic impedance on the PCB. Figure 21 shows the referenced CPWG RF trace design for an RF substrate with 12 mil thick Rogers RO4003 dielectric material. The RF trace with a 16 mil width and a 6 mil clearance is recommended for 2.2 mil finished copper thickness. Figure 21. Example PCB Stackup Figure 22 shows the routing of the RF traces, supply, and control signals from the ADRF5715. The ground planes are connected with as many filled through vias as allowed for optimal RF and thermal performance. The primary thermal path for the device is the bottom side. Figure 22. PCB Routings Figure 23 shows the recommended layout from the ATTIN and ATT- OUT pins of the ADRF5715 to the 50 Ω CPWG on the referenced stackup. PCB pads are drawn 1:1 to device pads. The ground pads are drawn solder mask defined, and the signal pads are drawn as pad defined. The RF trace from the PCB pad is extended with the same width 2 mils and tapered with 90° angle. The paste mask is also designed to match the pad without any aperture reduction. The paste is divided into multiple openings for the paddle. Figure 23. Recommended ATTIN Pin and ATTOUT Pin Transitions For alternate PCB stackups with different dielectric thickness and CPWG design, contact Analog Devices, Inc., Technical Support Request for further recommendations. |
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