74HC_HCT112

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Product data sheet

Rev. 3 — 9 August 2016

13 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 8.

Test circuit for measuring switching times

Table 9.

Test data

Type

Input

Load

Test

VI

tr, tf

CL

74HC112

VCC

6ns

15pF, 50 pF

tPLH, tPHL

74HCT112

3 V

6 ns

15 pF, 50 pF

tPLH, tPHL