ADF4002

Data Sheet

Rev. D | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

Timing Characteristics ................................................................ 4

 

Absolute Maximum Ratings............................................................ 5

 

Thermal Characteristics .............................................................. 5

 

ESD Caution.................................................................................. 5

 

Pin Configurations and Function Descriptions ........................... 6

 

Typical Performance Characteristics ............................................. 7

 

Theory of Operation ........................................................................ 8

 

Reference Input Section............................................................... 8

 

RF Input Stage............................................................................... 8

 

N Counter...................................................................................... 8

 

R Counter ...................................................................................... 8

 

Phase Frequency Detector (PFD) and Charge Pump.............. 8

 

MUXOUT and Lock Detect.........................................................9

 

Input Shift Register .......................................................................9

 

Latch Maps and Descriptions ....................................................... 10

 

Latch Summary........................................................................... 10

 

Reference Counter Latch Map.................................................. 11

 

N Counter Latch Map................................................................ 12

 

Function Latch Map................................................................... 13

 

Initialization Latch Map ............................................................ 14

 

Function Latch............................................................................ 15

 

Initialization Latch ..................................................................... 16

 

Applications..................................................................................... 17

 

Very Low Jitter Encode Clock for High Speed Converters... 17

 

PFD............................................................................................... 17

 

Interfacing ................................................................................... 17

 

PCB Design Guidelines for Chip Scale Package .................... 18

 

Outline Dimensions ....................................................................... 19

 

Ordering Guide .......................................................................... 19

 

REVISION HISTORY

9/15—Rev. C to Rev. D

Changed ADSP21xx to ADSP-2181............................ Throughout

Changes to Table 3............................................................................ 5

Changes to Figure 4.......................................................................... 6

Changes to Very Low Jitter Encode Clock for High Speed

Converters Section and Figure 20 ................................................ 17

Update Outline Dimensions ......................................................... 19

Changes to Ordering Guide .......................................................... 19

12/12—Rev. B to Rev. C

Change to Table 1 ............................................................................. 4

Added RFINA to RFINB Parameter, Table 3 .................................... 5

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 19

9/11—Rev. A to Rev. B

Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter

and Endnote 6, Table 1 .....................................................................4

Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 7,

Table 1 .................................................................................................4

Changes to Figure 4 and Table 5......................................................6

Updated Outline Dimensions....................................................... 19

4/07—Rev. 0 to Rev. A

Changes to Features List...................................................................1

Changes to Table 1.............................................................................3

Deleted Figure....................................................................................7

Changes to Figure 16...................................................................... 11

4/06—Revision 0: Initial Version