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HMC490LP5 データシート(PDF) 7 Page - Analog Devices

部品番号 HMC490LP5
部品情報  ACTIVE BIAS CONTROLLER
PDF  17 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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HMC490LP5 データシート(HTML) 7 Page - Analog Devices

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For price, delivery, and to place orders: Analog Devices, Inc., One Analog Way, Wilmington, MA 01887
Phone: 781-937-1428 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
Pin Descriptions
Pin Number
Function
Description
Interface Schematic
1, 5
VDD, VDIG
Bias supply Pin. Connect supply voltage
to this pin with appropriate filtering.
2
VG2CONT
Control voltage of the VG2. Use a resistor divider between
VDD and GND to set the voltage. VG2 is typically 1.3V
lower than the VG2CONT
10
VG2
Second gate control.
3
SW
Internal switch resistance control pin. If left floating, VSW
defaults to HIGH.
4
EN
Enable pin. System is enabled when Ven is HIGH (VDIG). If
left floating, Ven defaults to HIGH (enabled).
14
DISBLSC
Disables short circuit lock down when pulled to ground.
Leave it floating to enable short circuit lock down.
6
CPOUT
Negative voltage generator charge pump output. Negative
voltage generator needs a flying capacitor, a reservoir
capacitor and two diodes to operate. Please refer to the
application schematic for more info.
7
VGATEFB
Control pin for VGATEFB. Float VGATEFB when a
depletion mode transistor is biased. Selects the mode of
operation along with VNEGFB pin. For detailed usage
please refer to the Table 2.
8
VNEGFB
Feedback (Control) pin for Negative Voltage Generator
Charge Pump. Float to activate the negative voltage
generator / Sort to GND to disable the negative voltage
generator.
9
VNEG
Negative input to the chip. Should be supplied with CPOUT
when negative voltage generator is enabled, or connect to
external VSS when negative voltage generator is enabled.
For detailed usage please refer to the “Negative Voltage
Generator” section.
HMC981LP3E
v02.1222
ACTIVE BIAS CONTROLLER



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