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NRF24L01P-R データシート(PDF) 62 Page - Nordic Semiconductor |
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NRF24L01P-R データシート(HTML) 62 Page - Nordic Semiconductor |
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62 / 78 page ![]() Revision 1.0 Page 62 of 78 nRF24L01+ Product Specification N/A ACK_PLD 255:0 X W Written by separate SPI command ACK packet payload to data pipe number PPP given in SPI command. Used in RX mode only. Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled first in first out. N/A TX_PLD 255:0 X W Written by separate SPI command TX data pay- load register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only. N/A RX_PLD 255:0 X R Read by separate SPI command. RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX channels share the same FIFO. 1C DYNPD Enable dynamic payload length Reserved 7:6 0 R/W Only ‘00’ allowed DPL_P5 5 0 R/W Enable dynamic payload length data pipe 5. (Requires EN_DPL and ENAA_P5) DPL_P4 4 0 R/W Enable dynamic payload length data pipe 4. (Requires EN_DPL and ENAA_P4) DPL_P3 3 0 R/W Enable dynamic payload length data pipe 3. (Requires EN_DPL and ENAA_P3) Address (Hex) Mnemonic Bit Reset Value Type Description |
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