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PSD413A2 データシート(PDF) 87 Page - STMicroelectronics

部品番号 PSD413A2
部品情報  Low Cost Field Programmable Microcontroller Peripherals
PDF  123 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD413A2 データシート(HTML) 87 Page - STMicroelectronics

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PSD4XX Family
84
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t AVLX Time from Address Valid to ALE Invalid.
A – Address
L – Logic Level Low or ALE
T – R/W
C – Power Down
N – Reset
t – Time
D– Input Data
P – Port Signal
V – Valid
E –E
Q – Output Data
X – No Longer a Valid Logic Level
H – Logic Level High
R – WR, UDS, LDS, DS, IORD, PSEN
Z – Float
I – Interrupt
S – Chip Select
-70
-90*
-15
EPROM_CMiser
Symbol
Parameter
Conditions
Min Max Min Max Min Max
ON
Unit
tLVLX
ALE or AS Pulse Width
18
20
28
0
ns
tAVLX
Address Setup Time
(Note 3)
5
6
10
0
ns
tLXAX
Address Hold Time
(Note 3)
7
8
11
0
ns
tAVQV
Address Valid to Data
Valid
(Note 3)
70
90
150
Add 10
ns
t SLQV
CS Valid to Data Valid
80
100
150
Add 10
ns
RD to Data Valid
8/16-Bit Bus
(Note 1)
20
32
40
0
ns
t RLQV
RD to Data Valid 8-Bit
Bus, 8031 Separate
(Note 2)
32
38
45
0
ns
Mode
t RHQX
RD Data Hold Time
(Note 1)
0
0
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
30
32
38
0
ns
tRHQZ
RD to Data High-Z
(Note 1)
22
25
33
0
ns
tEHEL
E Pulse Width
30
32
38
0
ns
tTHEH
R/W Setup Time
to Enable
810
18
0
ns
tELTL
R/W Hold Time After
Enable
00
0
0
ns
In 16-Bit Data Bus
20
30
38
0
ns
tAVPV
Address Input Valid to
Mode (Note 9)
Address Output Delay
In 8-Bit Data Bus
22
32
48
0
ns
Mode (Note 9)
Read Timing (5 V ± 10% Versions)
NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals.
2. RD and PSEN have the same timing for 8031 mode.
3. Any input used to select an internal PSD4XX function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
*The -90 speed is available only on Industrial Temperature Range product.
13.8 Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions)



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