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ST5451 データシート(PDF) 26 Page - STMicroelectronics

部品番号 ST5451
部品情報  ISDN HDLC AND GCI CONTROLLER
PDF  34 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST5451 データシート(HTML) 26 Page - STMicroelectronics

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DYNAMIC ELECTRICAL CHARACTERISTICS - Double Clock Interface
Symbol
Parameter
Min.
Typ.
Max.
Unit
FSync
8 KHz
8
KHz
FCLK
16 x n x FSync 1
≤ n ≤ 64
128
8192
KHz
tWCH
Period of CLK High
50
ns
tWCL
Period of CLK Low
50
ns
tRC
Rise Time of CLK
10
ns
tFC
Full Time of CLK
10
ns
tHCF
Hold Time: CLK - FS
0
ns
tSFC
Set-up Time: FS - CLK
30
ns
tDCD
Delay Time: CLK High to data valid. out: 150 pF
80
ns
tDCZ
Delay Time: to Data Disabled
0
80
ns
tDFD
Delay Time: FSync. High to data valid. count: 150 pF. Applies
only if Sync rises later than CLK raising edge.
80
ns
tSDC
Set-up Time: Data valid to CLK receive edge.
30
ns
tHDC
Hold Time: CLK low to data invalid.
30
ns
ELECTRICAL CHARACTERISTICS - Single Clock Interface
Symbol
Parameter
Min.
Typ.
Max.
Unit
FSync
8 KHz
8
KHz
FCLK
8 x n x FSync 1
≤ n ≤ 64
64
4096
KHz
tWCH
Period of CLK High
80
ns
tWCL
Period of CLK Low
80
ns
tRC
Rise Time of CLK
10
ns
tFC
Full Time of CLK
10
ns
tHCF
Hold Time: CLK - FS
0
ns
tSFC
Set-up Time: FS - CLK
100
ns
tDCD
Delay Time: CLK High to data valid. out: 150 pF
80
ns
tDCZ
Delay Time: to Data Disabled
0
80
ns
tDFD
Delay Time: FSync. High to data valid. count: 150 pF. Applies
only if Sync rises later than CLK raising edge.
80
ns
tSDC
Set-up Time: Data valid to CLK receive edge.
30
ns
tHDC
Hold Time: CLK low to data invalid.
30
ns
ST5451
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