データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

L9805E データシート(PDF) 23 Page - STMicroelectronics

部品番号 L9805E
部品情報  Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver
PDF  127 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9805E データシート(HTML) 23 Page - STMicroelectronics

Back Button L9805E Datasheet HTML 19Page - STMicroelectronics L9805E Datasheet HTML 20Page - STMicroelectronics L9805E Datasheet HTML 21Page - STMicroelectronics L9805E Datasheet HTML 22Page - STMicroelectronics L9805E Datasheet HTML 23Page - STMicroelectronics L9805E Datasheet HTML 24Page - STMicroelectronics L9805E Datasheet HTML 25Page - STMicroelectronics L9805E Datasheet HTML 26Page - STMicroelectronics L9805E Datasheet HTML 27Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 127 page
background image
L9805E
Clocks, Reset, Interrupts & Power saving modes
23/127
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. The value to be stored in the CR register must be
between FFh and C0h (see Table 1):
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T5:T0 bit contain the number of increments which represents the time delay
before the watchdog produces a reset.
Note:
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Figure 9.
Functional Description
The Watchdog delay time is defined by bits 5-0 of the Watchdog register; bit 6 must always
be set in order to avoid generating an immediate reset. Conversely, this can be used to
generate a software reset (bit 7 = 1, bit 6 = 0).
The Watchdog must be reloaded before bit 6 is decremented to “0” to avoid a Reset.
Following a Reset, the Watchdog register will contain 7Fh (bits 0-7).
If the circuit is not used as a Watchdog (i.e. bit 7 is never set), bits 6 to 0 may be used as a
simple 7-bit timer, for instance as a real time clock. Since no reset will be generated under
these conditions, the Watchdog control register must be monitored by software.
Table 3.
Watchdog Timing (fOSC = 16 MHz)
WDG Register initial value
WDG timeout period (ms)
FFh
98.3
C0h
1.54
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
MSB
LSB
CLOCK DIVIDER
WDGF
WATCHDOG STATUS REGISTER (WDGSR)
WATCHDOG CONTROL REGISTER (WDGCR)
÷12288



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com