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ST72622L2M1L データシート(PDF) 22 Page - STMicroelectronics

部品番号 ST72622L2M1L
部品情報  LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI
PDF  132 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72622L2M1L データシート(HTML) 22 Page - STMicroelectronics

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Figure 18. Reset Timing Diagram
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-.
Figure 19. Reset Block Diagram
Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
VDD
OSCIN
fCPU
FFFF
FFFE
PC
RESET
tDDR
tOXOV
514 CPU
CLOCK
CYCLES
DELAY
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
200ns
Filter
tw(RSTL)out + 128 fOSC
delay



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