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ST92F120 データシート(PDF) 92 Page - STMicroelectronics |
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ST92F120 データシート(HTML) 92 Page - STMicroelectronics |
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92 / 320 page ![]() 92/320 ST92F120 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the correspond- ing WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: – If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are gener- ated. – If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. – If ID1S=0 and WKUP-INT=1 only a wake-up event is generated. – If ID1S=0 and WKUP-INT=0 neither interrupts on channel INTD1 nor wake-up events are gen- erated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7. If WUMx is reset, no wake-up events can be gen- erated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0). WAKE-UP MASK REGISTER LOW (WUMRL) R251 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUM[7:0]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the correspond- ing WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: – If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are gener- ated. – If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. – If ID1S=0 and WKUP-INT=1 only a wake-up event is generated. – If ID1S=0 and WKUP-INT=0 neither interrupts on channel INTD1 nor wake-up events are gen- erated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7. If WUMx is reset, no wake-up events can be gen- erated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0). 70 WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8 70 WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0 9 |
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