データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

ST92R195B データシート(PDF) 13 Page - STMicroelectronics

部品番号 ST92R195B
部品情報  ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
PDF  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92R195B データシート(HTML) 13 Page - STMicroelectronics

Back Button ST92R195B Datasheet HTML 9Page - STMicroelectronics ST92R195B Datasheet HTML 10Page - STMicroelectronics ST92R195B Datasheet HTML 11Page - STMicroelectronics ST92R195B Datasheet HTML 12Page - STMicroelectronics ST92R195B Datasheet HTML 13Page - STMicroelectronics ST92R195B Datasheet HTML 14Page - STMicroelectronics ST92R195B Datasheet HTML 15Page - STMicroelectronics ST92R195B Datasheet HTML 16Page - STMicroelectronics ST92R195B Datasheet HTML 17Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 18 page
background image
13/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
CURRENT CONSUMPTION
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)
Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.
The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.
2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to
VSS, HSYNC is driven by a 15625Hz clock.
All peripherals working including Display.
3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to
VSS, HSYNC is driven by a 15625Hz clock.
The TDSRAM interface and the Slicers are working; the Display controller is not working.
4. VSYN C and HSYNC tied to
VSS. External CLOCK pin (OSCIN) is held low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(V
DD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
TpC is the INTCLK clock period.
Symbol
Parameter
Conditions
Value
Unit
min
max
CIO
Pin Capacitance Digital Input/Output
10
pF
Symbol
Parameter
Condition s
Value
Unit
min
typ.
max
IDD1
Run Mode Current
notes 1,2; all On
70
100
mA
IDDA1
Run Mode Analog Current
(pin VDDA)
Timing Controller On
35
50
mA
IDD2
HALT Mode Current
notes 1,4
10
100
µA
IDDA2
HALT Mode Analog Current
(pin VDDA)
notes 1,4
40
100
µA
Symbol
Parameter
Condition s
Value
Unit
INTCLK=24 MHz.
min
max
TwLR
Low level pulse width
TpC+12
95
ns
TwHR
High level pulse width
TpC+12
95
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com